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Description: 该verilog代码位手动编写的异步fifo。-This code is manually generated asychronous fifo.
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Size: 3246080 |
Author: 江豪 |
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Description: FIFO Using MyFIFO_Block_Memory_v7_1
with verilog code
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Size: 288768 |
Author: amin |
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Description: 异步FIFO实现数据先入先出的存储方式基于verilog HDL语言-Asynchronous FIFO first-in, first-out data storage based on Verilog HDL language
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Size: 11264 |
Author: 章鱼 |
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Description: 同步与异步FIFO的verilog实现，包括源代码，testbench，测试以及综合通过，还有相关参考资料-Synchronous and asynchronous FIFO verilog achieve, including source code, testbench, test and integrated through, as well as related references
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Size: 1715200 |
Author: gt |
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Description: 红色飓风II开发板USB2FPGA USB驱动程序，由verilog编写，包括源码和FIFO测试程序-Red Hurricane II development board USB2FPGA USB driver from verilog preparation, including source code and test procedures FIFO
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Size: 3584000 |
Author: xueyuan |
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Description: Verilog编写的串口配合FIFO的代码，对大家学习串口和FIFO有一定帮助-Verilog prepared with FIFO serial code, we learn the serial port and FIFO have some help
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Size: 702464 |
Author: 李子豪 |
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Description: 同步FIFO源代码，使用Verilog编写，用户可以轻松转换成VHDL。-Synchronized FIFO source code
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Size: 1024 |
Author: 王敏志 |
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Description: 使用verilog语言编写的异步串口模块，带有16级深的FIFO，它与DSP28335的SCI相似，可以帮助初学者更快地理解FPGA和DSP的硬件结构和编程思路-Use verilog language of asynchronous serial port module, FIFO with deep level 16, it was similar with DSP28335 SCI, can help beginners to understand faster the FPGA and DSP hardware structure and programming ideas
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Size: 492544 |
Author: 夏小保 |
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Description: 用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。-Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.
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Size: 1441792 |
Author: 董明岩 |
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Description: 本代码用verilog语言，配合quartus里自带的fifo来简单实现vga显示屏的操作，重点在于弄清楚时序。代码中被注释的部分也可以用于彩色条纹的测试。-The code to use verilog language, with quartus in fifo comes to simply achieve vga screen operation, with emphasis on clear timing. The code portion of the notes can be tested for color stripe.
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Size: 7909376 |
Author: 普尔 |
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Description: 一个基于verilog的fifo的例子，由数据产生模块产生数据传到fifo中，然后同过发送模块将数据发到上位机上。-One based on the fifo verilog example, by the data generation module generates data to the fifo, and then sent over the same module sends data to the host computer.
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Size: 661504 |
Author: 陈栋磊 |
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Description: fifo 读写代码，能够进行速率匹配，很好的源代码-verilog hdl
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Size: 126976 |
Author: fengsen |
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Description: fx2lp 68013 xilinx XC3s400 实现slave fifo通讯，包括68013的固件以及fpga的代码（verilog）。摸了好久才调试通过的，特共享出来解救苍生！-fx2lp 68013 xilinx XC3s400 slave fifo
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Size: 888832 |
Author: jianhaoran |
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Description: 带fifo的串口通信verilog设计，该设计为学习uart所用，完成PC端发送至fpga后fpga原数据返回，支持长字符串。-Serial communication with fifo verilog design, which is used to learn uart complete PC sends data back to the original post fpga fpga, support long strings.
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Size: 150528 |
Author: Xin |
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Description: asynchronous fifo with pulse input
write by verilog code
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Size: 2048 |
Author: Long |
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Description: 基于IPcore的同步FIFO的设计。采用Verilog代码书写。读写位宽均为8bit，深度为32.-IPcore synchronous FIFO-based design. Using Verilog code writing. Read and write bits wide are 8bit, depth is 32.
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Size: 677888 |
Author: 杨杨 |
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Description: FIFO级联，利用verilog语言实现Xilinx FIFO18单元的多个级联，增大FIFO深度。-FIFO cascade, using Verilog Xilinx FIFO18 language to achieve a number of cascade units, increasing the FIFO depth.
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Size: 3072 |
Author: andThe |
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Description: verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
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Size: 2048 |
Author: dropins |
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Description: FIFO的verilog与VHDL的实现，并与FIFO的IP核做对比，为了方便大家学习，每个文件均附有测试脚本文件，希望对大家有用。-The FIFO verilog and VHDL implementation with FIFO IP core to do comparison, in order to facilitate learning, each file with a test script file, we want to be useful.
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Size: 234496 |
Author: 宋国志 |
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Description: verilog代码写的控制vga显示的实例，利用状态机进行描述，很好的参考例子-verilog language write serial fifo instance, because the serial port speed is relatively slow, a lot of the interface will use fifo buffer
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Size: 100352 |
Author: 崔帅 |
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